FIG. 1 schematically shows a processor array PA including 4×4 compute nodes N arranged in a network-on-chip of folded torus topology, as described in patent application US 20110058569. In an array topology, each node is connected to two other nodes in the same row and to two other nodes in the same column, through point-to-point bidirectional links. In a torus topology, the nodes of the array are also connected in a loop in each row and in each column, so that all nodes have the same physical structure as to their interconnections, including the nodes located at the edges of the array. In a folded topology, which is represented in FIG. 1, each node (unless it is located on the edge of array) is connected to two other nodes of same parity in the row and the column, so the links between nodes have substantially the same length.
Each node N includes a five way router which manages the four links, say North, South, East and West links, with the next nodes in the row and the column, and a link with a processing unit, for example a cluster of processors interconnected through a shared bus.
The processor array PA is fabricated as a single integrated circuit. To communicate with the outside world, it includes input/output IO units inserted in the network-on-chip at the edges of the array. As shown, such an IO unit may be provided at both ends of each row and each column. More specifically, each unit is inserted in the link connecting two extreme nodes N of a same row or a same column.
Each IO unit has a three-way router that manages the two links with nodes N and a link with an input/output interface. The input/output interface allows communication with the outside of the circuit through metal pads of the integrated circuit, intended to be put in contact with conductive tracks of a printed circuit board or other substrate.
To facilitate the programming of such a processor array, all compute nodes N have similar characteristics, allowing a development tool to map tasks, in automatic mode, on any of the nodes. To achieve this, the IO units are designed to be transparent to the internal communications of network-on-chip. Patent application US 20110058569 also describes a solution to reduce the latency through the routers of the IO units for internal communications.
For the purpose of standardization in marketing integrated circuits, the sizes of the processor array will be offered in a relatively narrow range. Thus, the computing power delivered by the largest array of the range is likely to be insufficient for more demanding applications.